Inputs
Component manifest, RTL, target constraints and tool configuration.
AccelFury
af — the AccelFury IP development toolchain
Development tools for FPGA IP checks and integration workflows.
Release status unconfirmed. Availability unconfirmed.
Status and access
- Stage
- Release status unconfirmed
- Access
- Availability unconfirmed
Current version, lifecycle and supported workflow matrix have not been independently confirmed.
License terms for the current distribution have not been confirmed. Discuss the intended use before evaluation.
Workflows
The source summary describes a manifest-first Rust CLI and the integrations below. These are reported workflows; current version support is unconfirmed.
| Workflow | Role | Evidence |
|---|---|---|
| Manifest-based project description | Component inputs and target configuration. | reported |
| Verilator simulation | Simulation integration. | reported |
| Yosys checks | RTL checks, separate from timing closure. | reported |
| FuseSoC packaging | Integration packaging, separate from board qualification. | reported |
Evaluation
Review the supplied version, supported target and tool versions before choosing a workflow.
Outputs
Check reports, build outputs and integration packages, according to the supplied workflow.
Current input schemas, commands and output formats need version-specific documentation. A successful build does not establish functional board behaviour.
Limitations
- No current installation command or evaluation package is confirmed.
- Workflow support depends on the supplied version and configuration.
- Integration with a tool does not establish support for every target.