Public IP cores
1 true IP core entry in /data/cores.json.
AccelFury
Portable FPGA IP cores for cryptography, DSP/audio and edge AI
Reusable RTL, an open toolchain and acceleration prototypes for teams that need deterministic hardware. Every claim links back to a public repo, test or measurement.
What is public
Public surface today
What is actually published. Numbers match github.com/AccelFury and /data/cores.json.
Open toolchain
af — Rust CLI for manifests, Verilator simulation, Yosys checks and FuseSoC packaging.
Template repository
core-template is a starter repository and example surface, separated from true IP catalog entries.
Release artifacts
0 published. Reviewable evidence lives in the repos.
Catalog
IP core categories
Filled categories ship today. Planned ones appear only when documented and verifiable.
Audio & signal processing
Streaming audio, PDM, PCM, filtering and signal-processing blocks with explicit clocking and verification status.
Planned categories: Cryptography · ZK-friendly primitives · Memory and streaming · Interfaces and protocol adapters · Bus bridges · Edge AI / DSP · Verification utilities · Board support wrappers.
Services
Commercial work
Engagement models around technical review, custom IP, licensing, support and R&D prototypes.
Custom FPGA IP development
Specification, RTL implementation, verification and integration support for workload-specific FPGA/IP cores.
FPGA acceleration feasibility review and prototyping
Workload analysis, architecture options, resource estimates, risk review and prototype planning for hardware acceleration projects.
Cryptography/ZK acceleration R&D
Research-track architecture review and prototype planning for NTT, MSM, hash pipelines and related proof-system bottlenecks.
Edge AI / DSP pipeline prototyping
Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks.
Commercial licensing and support
Commercial licensing discussions and paid support for integration, documentation, priority fixes and release-readiness review.