Audio & signal processing
Streaming audio, PDM, PCM, filtering and signal-processing blocks with explicit clocking and verification status.
AccelFury
FPGA IP cores and hardware acceleration prototypes for cryptography, signal processing and edge AI
AccelFury designs vendor-aware FPGA IP cores, RTL modules, verification assets and acceleration prototypes for teams that need deterministic hardware.
Catalog architecture
IP core categories
The site is structured as a platform catalog, not as a single-core landing page.
Cryptography
Cryptographic datapaths and primitives where public claims are tied to specifications, tests and measured evidence.
ZK-friendly primitives
Research and prototype work for field arithmetic, hashes, MSM, NTT and related proof-system bottlenecks.
Memory and streaming
FIFOs, stream adapters, buffering, backpressure handling and data-movement blocks.
Interfaces and protocol adapters
Board and subsystem adapters for protocol boundaries, handshakes and integration wrappers.
Bus bridges
Bridges between internal streams, memory-mapped buses and board-local integration boundaries.
Edge AI / DSP
Prototype dataflow for quantized inference, preprocessing and latency-sensitive DSP pipelines.
Verification utilities
Testbench helpers, debug wrappers, checkers and evidence packaging utilities.
Board support wrappers
Board-local wrappers and constraints that remain fail-closed until build and measurement evidence exist.
Other documented IP
Reserved for documented cores that do not fit an existing category. It should not be used to hide unclear status.
Engineering output
What we deliver
AccelFury sells reviewable engineering work: source, tests, docs, wrappers, licensing and support boundaries.
Engineering handoff
Work is scoped as reviewable artifacts that can be inspected, simulated, integrated and licensed.
- RTL/SystemVerilog/Verilog IP
- testbenches
- simulation scripts
- synthesis notes
- board integration notes
- wrappers
- documentation
- commercial licensing
- paid support
- architecture review
- feasibility reports
Trust model
Evidence-first engineering
Facts, limitations and verification state are visible before commercial discussion.
Claim boundary
Public claims must link to repo, docs, benchmark, measurement or release evidence.
- No fake benchmarks
- No unsupported pinouts
- No silent source-of-truth LLM content
- Every core has status, docs, limitations and verification level
Public core catalog
Current public assets
Public core data is available through the catalog and machine-readable JSON export.
Catalog status
1 public core entry is documented in the structured catalog. Open the catalog for names, status and evidence.
- Catalog entries are generated from /data/cores.json.
- Core-specific status and limitations stay in the catalog and detail pages.
Commercial work
Engagement models
Commercial work is framed around technical review, custom IP, licensing, support and R&D prototypes.
Custom FPGA IP development
Specification, RTL implementation, verification and integration support for workload-specific FPGA/IP cores.
FPGA acceleration feasibility review and prototyping
Workload analysis, architecture options, resource estimates, risk review and prototype planning for hardware acceleration projects.
Cryptography/ZK acceleration R&D
Research-track architecture review and prototype planning for NTT, MSM, hash pipelines and related proof-system bottlenecks.
Edge AI / DSP pipeline prototyping
Prototype FPGA dataflow for quantized inference paths, streaming DSP pipelines and latency-oriented preprocessing blocks.
Commercial licensing and support
Commercial licensing discussions and paid support for integration, documentation, priority fixes and release-readiness review.
Next step
Send workload, target board and constraints
The useful first message includes workload, board, interfaces, timing target, throughput target, power constraints and NDA requirements.