IP components
Reusable RTL for defined functions. Start with af-pdm-rx, a raw PDM receiver.
HARDWARE ACCELERATION + DEVELOPMENT TOOLS
Reusable IP and tools for specialized compute.
We develop hardware IP and tools, and help hardware teams adapt and integrate components. Our current work focuses on FPGA.
IP and tools for your hardware team.
af development toolchain
Development tools for FPGA IP checks and integration workflows.
Reusable logic. Target-specific integration.
Keep component logic separate from the interfaces, constraints and tools of each target.
- ComponentReusable logic and interfaces
- Target integrationWrappers, constraints and tools
- ResultsBuild outputs and test reports
Portability is assessed for each component, version and target. A shared interface alone does not establish support.
Start with a concrete data path.
Industrial and instrumentation
Sensor capture and streaming interfaces. Start with a suitable component or define an engineering project.
Edge AI and robotics
Evaluate sensor paths, preprocessing and integration. Feasibility and prototype work; no model-to-NPU compiler.
Cryptography and ZK
Study arithmetic and memory bottlenecks. Feasibility work; no accelerator product or hosted prover service.
Inside af-pdm-rx.
Capture raw PDM bits and pack them into a valid/ready stream.
No PCM conversion or CIC/FIR filtering. Simulation results are reported; functional board measurements are unconfirmed.
Next step
Bring a function. Define the result.
Agree the interfaces, target, deliverables and acceptance criteria. Start with a non-confidential summary.