af-pdm-rx
Portable Verilog-2001 raw PDM receiver core. Public repo, public docs and archived Tang Primer 20K Dock build evidence exist. Hardware-ready claims remain blocked on measured board evidence.
AccelFury
FPGA IP cores and hardware acceleration prototypes for cryptography, signal processing and edge AI
AccelFury is an evidence-first FPGA engineering project. Public work currently centers on af-pdm-rx, a Verilog raw PDM receiver IP core, plus research-track pages for ZK and edge-AI acceleration. Unsupported benchmarks, customer lists and production claims are intentionally omitted.
Proof point
Current public work
AccelFury currently has one public proof-point repository. The site does not claim a broader public product catalog than what is already visible.
Scope
What we build
The public site covers reusable FPGA IP, custom engineering services and research-track acceleration work.
FPGA IP cores
Reusable building blocks with documented interfaces, limitations and verification scope.
Custom RTL modules
Workload-specific datapaths, glue logic and timing-aware module boundaries for customer integrations.
Verification and testbenches
Simulation-first validation, handshake checks, reset tests and evidence packaging for release reviews.
Board bring-up support
Clocking, pin constraints, board wrappers, measurement plans and fail-closed bring-up workflows.
ZK acceleration prototypes
Research-track architecture work for proof-system bottlenecks and FPGA feasibility analysis.
DSP and edge AI pipelines
Prototype dataflow for preprocessing, quantized inference blocks and latency-sensitive FPGA pipelines.
Commercial model
Engagement models
Each engagement starts from a workload review, board assumptions and acceptance criteria rather than generic marketing promises.
Technical review
Available for technical review and scoping based on workload, board and integration constraints.
Custom FPGA IP development
Available for technical review and scoping based on workload, board and integration constraints.
Commercial license
Available for technical review and scoping based on workload, board and integration constraints.
Paid support
Available for technical review and scoping based on workload, board and integration constraints.
R&D prototype
Available for technical review and scoping based on workload, board and integration constraints.
Integration support
Available for technical review and scoping based on workload, board and integration constraints.
Trust
Evidence-first engineering
This site intentionally separates published evidence from planned or private work.
What is public now
Public GitHub organization, public af-pdm-rx repository, static docs, release evidence notes, licensing summary and a direct technical review contact path.
What is not public yet
No public ZK API, no named customer list, no published production benchmarks and no board-ready af-pdm-rx claim.
Evidence-first engineering
Public claims are limited to repo-visible docs, tests, constraints, release notes and measurement status.
- No unsupported pinout claims
- No unsupported benchmark ratios
- Testbench-first release discipline
- Reproducible reports and hashes
- Documented limitations and pending evidence
- Clear acceptance criteria for board claims
Research
Research directions
ZK and edge-AI pages are positioned as engineering and research capability pages, not as public production product claims.
ZK acceleration research
Research-track FPGA feasibility work for proof-system bottlenecks, with no public production API claims.
Edge AI and DSP research
Prototype-oriented FPGA dataflow work for quantized inference and streaming DSP pipelines.
Read or contact
Docs and next action
Public documentation, AI-readable indexes and the technical intake live under dedicated routes.
Engineering docs
Static documentation for af-pdm-rx, licensing, integration workflow and machine-readable indexes.
Technical intake
Send workload, target board, timing, throughput, power goals and NDA requirements for a technical review.
Next step
Send workload, target board and constraints
The fastest path to a useful review is a concise description of the workload, board, interfaces, timing target, throughput target, power constraints and NDA requirements.