IP components
Review the function, interfaces and evidence of each reusable RTL block.
HARDWARE ACCELERATION + DEVELOPMENT TOOLS
Reusable IP and tools for specialized compute.
Build hardware acceleration from reusable IP, explicit interfaces, and reviewable verification evidence. Design for portability by separating component logic from target integration. FPGA is our starting point.
FPGA today. Review current product status. Availability and verification are listed per component.
Stop rebuilding the integration layer.
Interfaces, build environments, target adaptation, and verification reports often need to be reconstructed when hardware is reused. AccelFury focuses on making those engineering boundaries explicit.
Reusable components. A consistent development workflow.
Combine a suitable IP component, development tooling and scoped engineering to address a defined integration problem.
af
A manifest-first development toolchain. Review access and workflow support before planning evaluation.
Scoped engineering
Agree target assumptions, deliverables and acceptance criteria for adaptation and integration.
Separate the component from the target.
Portability starts with separating reusable logic and component contracts from target-specific wrappers, constraints and tools.
- ComponentReusable RTL + component contract + verification assets
- Target flowWrappers, constraints and target-specific tools
- ReviewBuild outputs, reports and integration artifacts
Reuse is assessed per component, version and target. Each implementation needs its own build and verification evidence; support is never inferred from a shared interface.
FPGA is our current implementation foundation. Additional targets are a development direction, with support established only by component-specific evidence.
Start with a concrete data path.
Choose an initial scope around a function and acceptance criteria.
Industrial and instrumentation
Define a streaming interface, raw sensor capture or a bounded preprocessing function. Start with the raw PDM receiver where it fits; other functions require scoped engineering. No complete instrumentation system is offered.
Edge AI and robotics
Evaluate sensor data paths, preprocessing and integration against a target and operator set. The available offer is a scoped prototype or feasibility review; a model-to-NPU compiler is not offered.
Cryptography and ZK
Investigate a specific arithmetic or memory bottleneck through a feasibility study. No ready accelerator SKU or prover service is offered.
Inspect the engineering behind the component.
af-pdm-rx generates a microphone clock, samples raw PDM bits and packs them into a valid/ready stream.
Raw PDM, explicit boundaries
No PDM-to-PCM conversion, CIC/FIR or audio processing. Wrapper presence, builds and JTAG programming do not establish functional microphone measurements.
Reported simulation result
The historical record describes 13 Icarus test targets. Primary reports and the component revision have not been independently reviewed for this update.
Inspect evidence and limitationsIP components and the af toolchain.
Check the access route and product lifecycle before planning your evaluation.
IP components
Start with a bounded function and its interface contract. af-pdm-rx is a raw PDM receiver.
af — the AccelFury IP development toolchain
Manifest-first development tooling for FPGA IP workflows.
Define. Check. Build. Package. Review.
An engineering workflow starts with an explicit contract and ends with reviewable deliverables.
Confirm the component version, interfaces, target constraints and acceptance tests; run the supplied checks and target build; package the agreed integration assets; review results and gaps.
For af, individual command availability and target support require confirmation. Review the reported af workflows.
Integrate on agreed terms.
Scope, licensing, target assumptions, deliverables, acceptance and support terms are agreed for the engagement.
A manifest-first workflow for hardware teams.
Start with access, then review the component contract, checks and integration assumptions.
Next step
Bring a workload, interface, or integration problem.
Describe the function, interfaces, target, and acceptance criteria. Start without confidential design files.