[
  {
    "schemaVersion": 2,
    "id": "custom-fpga-ip-development",
    "kind": "service",
    "slug": "custom-fpga-ip-development",
    "title": "Custom FPGA IP development",
    "shortTitle": "Custom FPGA IP",
    "description": "Develop FPGA components with defined interfaces, tests and integration assets.",
    "status": "Available for technical review",
    "deliverables": [
      "spec",
      "RTL",
      "testbench",
      "docs",
      "integration wrapper",
      "simulation report",
      "optional board validation"
    ],
    "inputsRequired": [
      "Workload description",
      "Target FPGA or exact board",
      "Clocking and interface constraints",
      "Latency, throughput and power goals",
      "Verification and delivery requirements"
    ],
    "limitations": [
      "Performance guarantees depend on the exact workload, FPGA family and board constraints.",
      "Performance targets and measurement methods are agreed for the selected configuration."
    ],
    "clientProblem": "Develop FPGA components with defined interfaces, tests and integration assets.",
    "scope": "Implement a defined function in RTL, with agreed interfaces and integration assets.",
    "acceptanceCriteria": "Interface behaviour and agreed simulation tests pass for the specified configuration. Hardware measurements are included only when scoped.",
    "commercialModel": "Deliverables, milestones, licensing, support and payment terms are agreed per engagement.",
    "requestUrl": "/contact/?request=enterprise&service=custom-fpga-ip-development&source=services",
    "lastContentReviewedAt": "2026-09-26"
  },
  {
    "schemaVersion": 2,
    "id": "fpga-acceleration-prototyping",
    "kind": "service",
    "slug": "fpga-acceleration-prototyping",
    "title": "FPGA acceleration feasibility review and prototyping",
    "shortTitle": "Acceleration prototyping",
    "description": "Assess whether a workload fits FPGA acceleration before committing to implementation.",
    "status": "Available for technical review",
    "deliverables": [
      "workload analysis",
      "architecture options",
      "resource estimate",
      "risk matrix",
      "benchmark plan",
      "prototype plan"
    ],
    "inputsRequired": [
      "Algorithm or workload description",
      "Current software or hardware bottleneck",
      "Target device family or board",
      "Latency and throughput goals",
      "Data movement and host-interface assumptions"
    ],
    "limitations": [
      "Feasibility results are target-dependent and should be validated against board constraints.",
      "Benchmark plans are not benchmark results."
    ],
    "clientProblem": "Assess whether a workload fits FPGA acceleration before committing to implementation.",
    "scope": "Compare architecture options, resource estimates and implementation risks. RTL prototyping is a separately agreed deliverable.",
    "acceptanceCriteria": "The report answers the agreed feasibility questions and records assumptions, estimates, risks and a validation plan.",
    "commercialModel": "Deliverables, milestones, licensing, support and payment terms are agreed per engagement.",
    "requestUrl": "/contact/?request=enterprise&service=fpga-acceleration-prototyping&source=services",
    "lastContentReviewedAt": "2026-09-26"
  },
  {
    "schemaVersion": 2,
    "id": "cryptography-zk-acceleration-rd",
    "kind": "service",
    "slug": "cryptography-zk-acceleration-rd",
    "title": "Cryptography/ZK acceleration R&D",
    "shortTitle": "ZK acceleration R&D",
    "description": "Evaluate arithmetic and memory bottlenecks in proof systems, then define a prototype.",
    "status": "Research / prototype",
    "deliverables": [
      "primitive selection",
      "NTT/MSM/hash architecture sketch",
      "FPGA feasibility report",
      "prototype plan",
      "limitations"
    ],
    "inputsRequired": [
      "Proof system or primitive family",
      "Field size and arithmetic assumptions",
      "Memory topology or board assumptions",
      "Latency and throughput target"
    ],
    "limitations": [
      "Hosted proving and a complete ZK accelerator are outside this service.",
      "Speedup requires measurement on the selected workload and target."
    ],
    "clientProblem": "Evaluate arithmetic and memory bottlenecks in proof systems, then define a prototype.",
    "scope": "Select a proof-system bottleneck and compare arithmetic, memory and dataflow options.",
    "acceptanceCriteria": "The study documents the selected primitive, architecture options, resource estimates and proposed measurements.",
    "commercialModel": "Deliverables, milestones, licensing, support and payment terms are agreed per engagement.",
    "requestUrl": "/contact/?request=research&service=cryptography-zk-acceleration-rd&source=services",
    "lastContentReviewedAt": "2026-09-26"
  },
  {
    "schemaVersion": 2,
    "id": "edge-ai-dsp-pipeline-prototyping",
    "kind": "service",
    "slug": "edge-ai-dsp-pipeline-prototyping",
    "title": "Edge AI / DSP pipeline prototyping",
    "shortTitle": "Edge AI / DSP",
    "description": "Evaluate FPGA data paths for sensor preprocessing, streaming DSP and selected inference operators.",
    "status": "Research / prototype",
    "deliverables": [
      "dataflow design",
      "quantization assumptions",
      "latency estimate",
      "target board constraints",
      "prototype RTL/HLS plan"
    ],
    "inputsRequired": [
      "Model, operator set or DSP chain",
      "Precision and quantization assumptions",
      "Input/output bandwidth",
      "Target board or device family"
    ],
    "limitations": [
      "A complete inference appliance and model-to-NPU compiler are outside this service.",
      "Power and throughput depend on board power delivery, memory topology and the exact operator mix."
    ],
    "clientProblem": "Evaluate FPGA data paths for sensor preprocessing, streaming DSP and selected inference operators.",
    "scope": "Evaluate an operator set or DSP chain against precision, bandwidth and board constraints.",
    "acceptanceCriteria": "The deliverable records the dataflow, quantization assumptions, latency estimate and target constraints. Prototype RTL requires a separate agreed scope.",
    "commercialModel": "Deliverables, milestones, licensing, support and payment terms are agreed per engagement.",
    "requestUrl": "/contact/?request=research&service=edge-ai-dsp-pipeline-prototyping&source=services",
    "lastContentReviewedAt": "2026-09-26"
  },
  {
    "schemaVersion": 2,
    "id": "commercial-licensing-support",
    "kind": "service",
    "slug": "commercial-licensing-support",
    "title": "Commercial licensing and support",
    "shortTitle": "Licensing and support",
    "description": "Agree usage rights and integration support for an existing component.",
    "status": "Available by direct request",
    "deliverables": [
      "private license discussion",
      "integration help",
      "priority fixes",
      "documentation support",
      "release-readiness review"
    ],
    "inputsRequired": [
      "Intended use case",
      "License scope",
      "Support expectations"
    ],
    "limitations": [
      "Closed-source, proprietary or customer-delivered bitstream use requires a separate commercial agreement."
    ],
    "clientProblem": "Agree usage rights and integration support for an existing component.",
    "scope": "Review rights and support for an existing component. New component development is a separate engagement.",
    "acceptanceCriteria": "The agreement identifies the component, permitted use, delivery terms and support responsibilities.",
    "commercialModel": "Deliverables, milestones, licensing, support and payment terms are agreed per engagement.",
    "requestUrl": "/contact/?request=licensing&service=commercial-licensing-support&source=services",
    "lastContentReviewedAt": "2026-09-26"
  }
]